Semiconductor memory device, method of manufacturing the same and method of forming contact structure
US8912655B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2012 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | May 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.