Methods and apparatus for performing wafer-level testing on antenna tuning elements
US8912809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2012 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Jan 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/21
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A test system for testing an antenna tuning element is provided. The test system may include a tester, a test fixture, and a probing structure. The probing structure may include probe tips configured to mate with corresponding solder bumps formed on a device under test (DUT) containing an antenna tuning element. The DUT may be tested in a shunt or series configuration. The tester may be electrically coupled to the test probe via first and second connectors on the test fixture. An adjustable load circuit that is coupled to the second connector may be configured in a selected state so that a desired amount of electrical stress may be presented to the DUT during testing. The tester may be used to obtain measurement results on the DUT. Systematic effects associated with the test structures may be de-embedded from the measured results to obtain calibrated results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.