Clocked charge domain logic
US8912814B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2013 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Jun 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.