Low power quadrature waveform generator
US8912836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2013 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Jul 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.