Power amplifier circuit and front end circuit
US8912847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2009 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Jun 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0408
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S_DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S_DR) into a first and second signal (S—1, S—2). The first signal (S—1) is associated to a first predetermined and the second signal (S—2) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA1, PA2). The first and second power amplifier stage (PA1, PA2) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA1, PA2) is operable to provide a first and second amplified signal (S_A1, S—2), respectively, dependent on the first and second signal (S—1, S—2), respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.