Fault tolerant managed switching element architecture
US8913483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Mar 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2101/622
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a hierarchical switching architecture that includes at least one lower level managed switching element that connects to several higher level managed switching elements, some embodiments provide a method of identifying a higher level managed switching element to which the lower level managed switching element forwards a packet for further processing. The method computes a value based on a set of attributes of the packet. The method identifies a record from a hierarchy traversal table based on the computed value. The record specifies (1) a first higher level managed switching element as a primary higher level managed switching element and (2) a second higher level managed switching element as a secondary higher level managed switching element. The primary and secondary higher level managed switching elements are for forwarding the packet for further processing. The method forwards the packet to one of the higher level managed switching elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.