Patent · US Active

Integrated circuit, system, and method including a shared synchronization bus

US8914563B2 · kind B2 · utility

2Cited by

3References

19Claims

0Family size

Assignee

Silicon Laboratories Inc. · US

Inventors

Bradley Martin · Austin, US
Thomas Saroshan David · Austin, US
Alan L. Westwick · Austin, US

Key dates

Filing date	Feb 28, 2012
Grant date	Dec 16, 2014
Priority date	—
Expiry date	Jun 4, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/385
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.