Bios controlled peripheral device port power
US8914649B2 · kind B2 · utility
27Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2009 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Aug 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3293
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device (101, 400, 500) has a processor (401) and at least one peripheral device port (106, 107, 108, 109, 410-1 to 410-5). The processor (401) is configured to selectively power the at least one peripheral device port (106, 107, 108, 109, 410-1 to 410-5) when the processor (401) is in a sleep state (302, 303, 304, 305, 306) according to at least one setting stored by firmware (405) of the processor (401).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.