Noise filtering circuit and operating method thereof
US8917138B2 · kind B2 · utility
0Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2013 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Feb 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There are provided a noise filter circuit and an operating method thereof. A noise filter circuit includes a first delay circuit, and a second delay circuit connected to the first delay circuit in series, wherein the first delay circuit and the second delay circuit each include at least one inverter and at least one delay element for generating a predetermined delay, and the first delay circuit and the second delay circuit have different filtering characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.