Circuit which performs split precision, signed/unsigned, fixed and floating point, real and complex multiplication
US8918445B2 · kind B2 · utility
17Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2011 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Nov 27, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.