Memory controller, memory system, semiconductor integrated circuit, and memory control method
US8918589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2009 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Feb 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.