Enforcing system intentions during memory scheduling
US8918595B2 · kind B2 · utility
8Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2011 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Aug 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller receives memory access requests from a host terminal, the memory access requests from the host terminal including one or both of host read requests and host write requests. The memory controller generates memory access requests. Priorities are assigned to the memory access requests. The memory access requests are segregated to memory unit queues of at least one set of memory unit queues, the set of memory unit queues associated with a memory unit. Each memory access request is sent to the memory unit according to a priority and an assigned memory unit queue of the memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.