Non-concatenated FEC codes for ultra-high speed optical transport networks
US8918694B2 · kind B2 · utility
11Cited by
2References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2012 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | May 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.