Decoding method and apparatus for non-binary, low-density, parity check codes
US8918704B2 · kind B2 · utility
2Cited by
6References
13Claims
0Family size
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1171
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute dc output vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.