Process for providing electrical connections with reduced via capacitance on circuit boards
US8918991B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2011 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jun 19, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to circuit boards and, more specifically, a process for providing electrical connections with reduced via capacitance on circuit boards. In one embodiment, the present invention provides a method for providing an electrical connection between traces disposed on different layers of a circuit board, the method comprising forming in the board a via hole that extends between the different layers and interconnects a pair of electrically conductive traces disposed on the different layers. An inner sidewall of the via hole includes electrically conductive material thereon. The method further comprises removing a first portion of the conductive material from the inner sidewall by removing a first portion of the inner sidewall. A remaining portion of the conductive material on a remaining portion of the inner sidewall interconnects the pair of traces and has a corresponding width that is substantially similar to a width of each trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.