Semiconductor device having mode of operation defined by inner bump assembly connection
US8921158B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Sep 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/17106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices are described that are configured to have a state of operation defined by a connection between at least one inner bump assembly and a selected outer bump assembly. In an implementation, the semiconductor device, which may be a wafer-level (chip-scale) package semiconductor device, includes an integrated circuit chip, a plurality of outer bump assemblies disposed on the chip, and one or more inner bump assemblies disposed on the chip so that the inner bump assemblies are at least partially surrounded by the outer bump assemblies. At least one of the inner bump assemblies is configured to be connected to a selected outer bump assembly to cause the integrated circuit chip to have a desired state of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.