Thin film transistor array panel and method of manufacturing the same
US8921852B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jun 11, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jun 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0231
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor array panel includes: a substrate, a gate line positioned on the substrate and including a gate electrode, a semiconductor layer positioned on the substrate and including an oxide semiconductor, a data wire layer positioned on the substrate and including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, and a capping layer covering the data wire layer, in which an end of the capping layer is inwardly recessed as compared to an end of the data wire layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.