MOS P-N junction diode with enhanced response speed and manufacturing method thereof
US8921949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Apr 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.