Memory device using flag cells and system using the memory device
US8923043B2 · kind B2 · utility
2Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jun 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a normal cell which is configured to be programmed to a first resistance and stabilized as a resistance of the normal cell drifts from the first resistance to a second resistance; a flag cell which is configured to be programmed to a third resistance smaller than the first resistance and stabilized as a resistance of the flag cell drifts from the third resistance to a fourth resistance smaller than the second resistance; and a decision circuit which is configured to decide whether the flag cell has been stabilized in order to determine whether the normal cell has been stabilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.