Semiconductor memory device
US8923074B2 · kind B2 · utility
2Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Dec 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.