Data transmission involving multiplexing and demultiplexing of embedded clock signals
US8923347B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2010 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Oct 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data transmission system, a first node receives at least two sets of input data signals including at least two signals being based on different synchronization sources. The first node extracts a respective clock signal representing the embedded clock signals from the sources, samples and formats these signals for transmission according to a TDM structure. The TDM formatted signals are transmitted as at least one bit stream over a transmission medium to at least one second node, where the bit stream is demultiplexed into at least two sets of output data signals respective demultiplexed clock signals representing the sampled clock signals. A jitter attenuating mechanism reduces an amount of frequency jitter to below a predefined level to produce a respective clock signal having a synchronization quality superior to that of the demultiplexed clock signals. An interface module recombines each data signal with its associated clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.