Circuitry for padded communication protocols
US8923440B1 · kind B1 · utility
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11References
34Claims
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Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Mar 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0064
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.