Image processing circuit and image processing method
US8923643B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Apr 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/51
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image processing circuit and an image processing method are disclosed. The image processing circuit comprises a block matching unit, a multiplexer, an arbiter, and a motion compensation circuit. The block matching unit calculates an alternating current (AC) sum of absolute difference (SAD) and a direct current (DC) sum of absolute difference (SAD) according to a current block in a current image and a reference block in a reference image. The arbiter controls the multiplexer selectively to output the AC SAD or the DC SAD according to an arbitration rule related to a scene characteristic of the current image. The motion compensation circuit executes motion compensation according to the AC SAD or the DC SAD outputted by the multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.