Methods and system for erasing data stored in nonvolatile memory in low power applications
US8924633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Feb 21, 2033 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF15B2211/7055
- WIPO fieldMechanical elements
- WIPO sectorMechanical engineering
Abstract
The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.