Inter-processor communication channel including power-down functionality
US8924768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Aug 2, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.