System and method for cycle slip correction
US8924823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jul 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3854
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system and method including a parity bit encoder for encoding each n bits of data to be transmitted with a parity check bit to produce blocks of n+1 bits (n information bits plus one parity bit associated with the n information bits). Each of the blocks of n+1 bits are Gray mapped to a plurality of associated QAM symbols that are modulated onto an optical wavelength and transmitted to a receiver. A maximum a posteriori (MAP) decoder is used at the receiver to correct for cycle slip. Phase errors of 180 degrees may be detected by independently encoding odd and even bits prior to Gray mapping, and identifying errors in decoding odd numbered bits at the receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.