Error correction circuit for data communication providing parallelizable linear programming decoding
US8924834B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
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Key dates
| Filing date | Sep 26, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error detection/correction system provides an electronic circuit detecting and correcting transmission errors using linear programming. Linear programming techniques are made practical for real-time error correction and decoding by dividing the linear programming problem into independent parallelizable problems so that separate independent portions of the electronic circuit may simultaneously address solutions related to individual bits and/or parity rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.