Semiconductor device having plural memory chip
US8924903B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2011 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Dec 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.