Method of manufacturing a non-volatile memory device having a vertical structure
US8927366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Apr 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
Abstract
A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.