Systems and methods for reducing contact resistivity of semiconductor devices
US8927418B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.