Self-aligned patterning technique for semiconductor device features
US8927425B1 · kind B1 · utility
6Cited by
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1Claims
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Key dates
| Filing date | Aug 19, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Aug 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device utilizing a plurality of masks and spacers. The method includes forming parallel first trenches in a substrate using a first lithographic process. The substrate includes sidewalls adjacent to the parallel first trenches. Forming first spacers adjacent to the sidewalls. Removing the sidewalls, which in part includes using a second lithographic process. Forming second spacers adjacent to the first spacers, resulting in spacer ridges. Etching portions of the substrate between the spacer ridges resulting in second trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.