Patent · US Active

Heterostructure power transistor with AlSiN passivation layer

US8928037B2 · kind B2 · utility

8Cited by

84References

23Claims

0Family size

Assignee

POWER INTEGRATIONS, INC. · US

Inventors

Jamal Ramdani · Gilbert, US
Michael Murphy · Long Beach, US
John Paul Edwards · Fryeburg, US

Key dates

Filing date	Feb 28, 2013
Grant date	Jan 6, 2015
Priority date	—
Expiry date	Feb 28, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/691
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.