Current-mode-logic devices resistant to single event disturbances
US8928348B1 · kind B1 · utility
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8References
19Claims
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Key dates
| Filing date | Nov 6, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jan 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09432
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current-mode-logic gate designed to have a first electronic path and a second electronic path. Each electronic path has a pair of transistors. The second electronic path is physically separated and identical to the first electronic path. In operation, a first input signal is transmitted through the first electronic path of the current-mode-logic gate to produce a first output signal. Similarly, a second input signal is transmitted through the second electronic path of the current-mode-logic gate to produce a second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.