High frequency smart buffer
US8928360B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Apr 1, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Apr 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/3089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.