Low power local oscillator quadrature generator
US8928369B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jul 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.