Programmable delay generator and cascaded interpolator
US8928384B2 · kind B2 · utility
2Cited by
14References
9Claims
0Family size
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Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Dec 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00065
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.