Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
US8928507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jul 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W56/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may include a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.