Sigma-delta modulator with SAR ADC and truncater and related sigma-delta modulation method
US8928511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jun 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3042
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.