Shift register, gate driver on array panel and gate driving method
US8928573B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Feb 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The embodiment of the present invention discloses a shift register for reducing the power consumption during driving. The shift register includes a protection circuit, a retaining circuit, an output circuit, a first driving circuit, a second driving circuit, a resetting circuit, a timing control terminal, a first power supply terminal, a second power supply terminal, a third power supply terminal and a fourth power supply terminal. The embodiment of the present invention further discloses a Gate driver On Array (GOA) panel and a method for gate driving.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.