Cache memory controller and method for replacing a cache block
US8930630B2 · kind B2 · utility
4Cited by
5References
4Claims
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Assignee
Inventor
Key dates
| Filing date | Sep 2, 2009 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Feb 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.