Reducing read latency using a pool of processing cores
US8930633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jun 27, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a read processing storage system, using a pool of CPU cores, the CPU cores are assigned to process either write operations, read operations, and read and write operations, that are scheduled for processing. A maximum number of the CPU cores are set for processing only the read operations, thereby lowering a read latency. A minimal number of the CPU cores are allocated for processing the write operations, thereby increasing write latency. Upon reaching a throughput limit for the write operations that causes the minimal number of the plurality of CPU cores to reach a busy status, the minimal number of the plurality of CPU cores for processing the write operations is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.