Multiprocessor computer system with reduced directory requirement
US8930640B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Feb 6, 2009 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Nov 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention has application in implementation of large Symmetric Multiprocessor Systems with a large number of nodes which include processing elements and associated cache memories. The illustrated embodiment of the invention provides for interconnection of a large number of multiprocessor nodes while reducing over the prior art the size of directories for tracking of memory coherency throughout the system. The embodiment incorporates within the memory controller of each node, directory information relating to the current locations of memory blocks which allows for elimination at a higher level in the node controllers of a larger volume of directory information relating to the location of memory blocks. This arrangement thus allows for more efficient implementation of very large multiprocessor computer systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.