High-speed LDPC decoder
US8930789B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jul 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices are described for decoding data using a low-density parity check (LDPC) decoder. An edge memory in the LDPC decoder is configured to have a first bank and a second bank of memory partitions. The first bank stores extrinsic information for edges for a first set of N check nodes and the second bank stores extrinsic information for edges for a second set of N check nodes. The first and second banks are concurrently accessed to process 2N check nodes in parallel. The first and second sets of N check nodes may respectively correspond to odd-numbered and even-numbered check nodes from the 2N check nodes processed in parallel by the LDPC decoder. The LDPC decoder operation may include initializing channel soft information into a memory different from the edge memory and the use of incremental changes in the extrinsic information to update the extrinsic information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.