Patent · US Active

Method of forming an electrical contact between a support wafer and the surface of a top silicon layer of a silicon-on-insulator wafer and an electrical device including such an electrical contact

US8932942B2 · kind B2 · utility

1Cited by

0References

10Claims

0Family size

Assignee

TEXAS INSTRUMENTS DEUTSCHLAND GMBH · DE

Inventors

Philipp Steinmann · Richardson, US
Manfred Schiekofer · Freising, DE
Michael Kraus · Ehrenkirchen, DE
Thomas Scharnagl · Perchtoldsdorf, AT
Wolfgang Schwartz · Hamburg, DE

Key dates

Filing date	Mar 23, 2010
Grant date	Jan 13, 2015
Priority date	—
Expiry date	Mar 23, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/01
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.