Hybrid analog-to-digital converter having multiple ADC modes
US8933385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2012 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | May 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/56
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.