High capacity select switches for three-dimensional structures
US8933516B1 · kind B1 · utility
24Cited by
19References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Jun 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/845
Abstract
A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.