Integrated circuit stack with integrated electromagnetic interference shielding
US8933544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2012 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Apr 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/018
Abstract
An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.