Level shift circuit using parasitic resistor in semiconductor substrate
US8933714B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shift circuit in which no adverse effect is produced on a delay time, regardless of the resistance values of resistors. The level shift circuit includes an operation detection circuit that outputs a nseten signal and a nresen signal in response to a state of output from first and second series circuits, a latch malfunction protection circuit connected to the operation detection circuit, a latch circuit connected through first to sixth resistors to first and second level shift output terminals of the first and second series circuits, first and second parasitic resistors, and third and fourth switching elements connected in parallel therewith, and fifth and sixth switching elements connected to a power source potential, a connection point of the first and second resistors or a connection point of the third and fourth resistors, and the operation detection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.