Patent · US Active

Clock generation circuit

US8933735B2 · kind B2 · utility

1Cited by

4References

3Claims

0Family size

Assignee

Thomson Licensing · FR

Inventors

Holger Kropp · Großburgwedel, DE
Herbert Schuetze · Celle, DE
Stefan Abeling · Winsen (Aller), DE

Key dates

Filing date	Jul 12, 2012
Grant date	Jan 13, 2015
Priority date	—
Expiry date	Jul 12, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/0814
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock generation circuit comprises an internal clock signal source providing an internal clock signal and a synchronization device for synchronization the internal clock signal with a reference clock signal provided externally from the clock generation circuit. The synchronization device comprises n delay locked loop circuits, n being an integer greater than 1, each delay locked loop circuit having a clock input for receiving the internal clock signal and a clock output for providing an output clock signal with an individual phase shift that is adjustable. The synchronization device further comprises a multiplexer having n inputs and an output wherein each of the n inputs is connected to an output of one of the n delay locked loops and a control circuit. The control circuit is adapted to adjust at least one of the delay locked loop circuits for providing an individual phase shift according to a current phase shift and to select that input of the multiplexer that receives an output clock signal of the adjusted delay locked loop circuit that is synchronized in frequency and phase with the reference clock signal, wherein the output of the multiplexer provides that output clock signa…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.