Method and apparatus for generating delay
US8933741B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2010 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Jan 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00228
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide an integrated circuit having a delay element that is configured as a complementary voltage based current starved delay element. The delay element drives an output node to generate an output signal in response to an input signal received at an input node. The delay element includes a first switch transistor configured to switch on in response to the input signal satisfying a switching condition, and a second switch transistor configured to switch on in response to the input signal satisfying the switching condition. The first switch transistor drives the output node with a first current that is controlled by a first bias voltage. The second switch transistor drives the output node with a second current that is controlled by a second bias voltage. The first bias voltage and the second bias voltage are complementary. In an example, both the first switch transistor and the second switch transistor are NMOS transistors. In another example, both the first switch transistor and the second switch transistor are PMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.